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Re: Qemu for MIPS

To: Dominic Sweetman <dom@mips.com>
Subject: Re: Qemu for MIPS
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 13 Jun 2005 13:56:10 +0100
Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org, Jocelyn Mayer <l_indien@magic.fr>, Fabrice Bellard <fabrice@bellard.org>
In-reply-to: <17069.29065.124810.728626@gargle.gargle.HOWL>
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References: <20050613105944.GA19704@linux-mips.org> <17069.29065.124810.728626@gargle.gargle.HOWL>
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On Mon, Jun 13, 2005 at 12:44:09PM +0100, Dominic Sweetman wrote:

> > Known bugs:
> > 
> >  o ll/sc don't use a ll_bit like the real hardware thus right now any atomic
> >    functions aren't really atomic.
> 
> I suppose you know that the CPUs all implement "break link on
> exception" by zeroing the link bit on an 'eret'?  That doesn't sound
> too hard...

It's not hard to add the llbit indeed - maybe I'm trying to hard to be
obscure use compatible.  Generally Qemu is trading the highest accuracy
of emulation for speed ...

> Arguably, an emulator should not provide the LLaddr register at all.
> It's optional and "only available for debug" - and probably such
> debugging is possible another way in an emulator.  Robust software
> shouldn't depend on assuming the contents make sense.

The only use I've seen for this register is having it being used as a
cp0 scratch register allowing to save the entire 31 GPRs.  Very old
Linux/MIPS used to do that but it doesn't match the reality of MIPS ABIs,
so I gave up on that very soon.  Like 11 years agp :)

> Not quite there yet... but well done, again.

  Ralf

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