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RE: ATA devices attached to arbitary busses

To: Bryan Althouse <bryan.althouse@3phoenix.com>
Subject: RE: ATA devices attached to arbitary busses
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Fri, 6 May 2005 18:47:41 +0200 (CEST)
Cc: "'Alan Cox'" <alan@lxorguk.ukuu.org.uk>, Linux/MIPS Development <linux-mips@linux-mips.org>
In-reply-to: <20050506152006Z8225995-1340+6646@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050506152006Z8225995-1340+6646@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Fri, 6 May 2005, Bryan Althouse wrote:
> All IDE drives should have the identical memory map.  But, the kernel does
> not communicate directly with the drive, it communicates though an IDE host
> adaptor (which may have different implementations).  If the host adaptor's
> memory map "matches" that of the IDE drive spec, then you consider it to be
> a "standard port layout"?  Since my host adaptor will be implemented in an
> FPGA, if I give it the IDE memory map defined in ide.h, then your example
> code will be applicable.
> 
> The memory map defined in ide.h makes sense to me (it seems to match the IDE
> drive memory map) until we get down to offset 6 (IDE_SELECT_OFFSET).  From
> here down, I have trouble matching the #define names with the register
> names/descriptions from the IDE spec.  Also, I am puzzled as to why there
> are 10 registers defined in ide.h when my IDE spec only shows 9.  The IDE
> spec that I am referencing looks like this:
> 
> CS0   CS1    DA2   DA1   DA0   READ              WRITE
> A     N      0     0     0     Data              Data
> A     N      0     0     1     Error             Features
> A     N      0     1     0     Sector Count      Sector Count
> A     N      0     1     1     Sector Number     Sector Number
> A     N      1     0     0     Cylinder Low      Cylinder Low
> A     N      1     0     1     Cylinder High     Cylinder High
> A     N      1     1     0     Device/Head       Device/Head
> A     N      1     1     1     Status            Command
> N     A      1     1     0     Alternate Status  Device Control (IRQ en/dis)
> 
> 
> ide.h shows the following offsets:
> 
> #define IDE_DATA_OFFSET               (0)
> #define IDE_ERROR_OFFSET      (1)
> #define IDE_NSECTOR_OFFSET    (2)
> #define IDE_SECTOR_OFFSET     (3)
> #define IDE_LCYL_OFFSET               (4)
> #define IDE_HCYL_OFFSET               (5)
> #define IDE_SELECT_OFFSET     (6)
> #define IDE_STATUS_OFFSET     (7)
> #define IDE_CONTROL_OFFSET    (8)
> #define IDE_IRQ_OFFSET                (9)
> 
> Do you know of an IDE host adapter chipset which is standard?  If someone
> knows of a part number, I could look up its datasheet.  This would probably
> clear up my confusion.  Thanks again!  

This is not the direct `memory map' of the IDE drive's registers! It's an
indirect map, cfr. e.g.

    #define IDE_DATA_REG            (HWIF(drive)->io_ports[IDE_DATA_OFFSET])

So the actual register is found by looking up offset IDE_DATA_OFFSET in the
array HWIF(drive)->io_ports[].

Gr{oetje,eeting}s,

                                                Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                                            -- Linus Torvalds

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