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Re: preempt safe fpu-emulator

To: kevink@mips.com
Subject: Re: preempt safe fpu-emulator
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Fri, 29 Apr 2005 22:40:24 +0900 (JST)
Cc: ralf@linux-mips.org, linux-mips@linux-mips.org
In-reply-to: <004e01c54c0c$4c9f3d30$10eca8c0@grendel>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <002d01c54bfa$5b913f80$0deca8c0@Ulysses> <20050428152123.GH1276@linux-mips.org> <004e01c54c0c$4c9f3d30$10eca8c0@grendel>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Thu, 28 Apr 2005 18:06:53 +0200, "Kevin D. Kissell" <kevink@mips.com> 
>>>>> said:

kevink> The global variable thing was clearly not SMP safe - but then
kevink> again, the 32-bit MIPS kernel we were working with wasn't SMP
kevink> safe either, in those days.  ;o)

Also, IIRC, old FPU ownership management ("lazy fpu switch") was
somewhat broken (or fragile at least) in those days.  The current code
is more robust (and simple, I suppose).

kevink> But *if* - and it may not really (or no longer) be the case -
kevink> there is an implicit assumption that some FCSR state is
kevink> preserved on a context switch, it would be more correct to map
kevink> the ieee754_csr symbol to a per-CPU variable than a per-thread
kevink> variable.

Thanks for your advise.  I believe there is not a such assumption now.
Any newly created process always start with CP1 disabled, and on the
first CP1 unusable exception FCSR will be initialized to 0.

---
Atsushi Nemoto

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