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Re: memcpy prefetch

To: Dominic Sweetman <dom@mips.com>
Subject: Re: memcpy prefetch
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 7 Apr 2005 15:05:07 +0100
Cc: Greg Weeks <greg.weeks@timesys.com>, linux-mips@linux-mips.org
In-reply-to: <16981.10097.547098.639380@arsenal.mips.com>
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References: <4253D67C.4010705@timesys.com> <20050406200848.GB4978@linux-mips.org> <4255240E.4050701@timesys.com> <16981.10097.547098.639380@arsenal.mips.com>
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On Thu, Apr 07, 2005 at 01:28:33PM +0100, Dominic Sweetman wrote:

> Greg Weeks (greg.weeks@timesys.com) writes:
> 
> > What's the performance hit for doing a pref on a cache line that is 
> > already pref'd? Does it turn into a nop, or do we get some horrible 
> > degenerate case?
> 
> The specification for the prefetch instruction is fairly wide, to
> permit different implementations to act differently.  It's perfectly
> legal for it to be a no-op.

The R5000 series actually treats it as a nop - which is why Linux treats
the R5000 as a CPU that does not have prefetch.

>  However, implementors are told that they
> should not do anything which would make performance *worse* than if it
> was a no-op.

Okay, but that should be obvious, I'd hope :-)

> > Are 64 bit processors always at least 32 byte cache line size?
> 
> There's no reliable correlation.  If you were to go round the
> "autogenerated at kernel-startup-time" route, then you can figure out
> the line size from the "Config" registers (MIPS32- or MIPS64-compliant
> CPUs) or from a table of CPU IDs or otherwise (earlier CPUs)...

Linux already contains a huge chunk of code to detect these and many
more cache properties for mips32, mips64 and more.  We also try to make
sure the compiler can do constant folding etc. as far as possible for
a particular platform.  All it takes is a suitable cpu-feature-overrides.h.
In absence of that Linux will built cache that pretty much support
everything in the universe - at some code bloat.

  Ralf

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