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Re: memcpy prefetch

To: Greg Weeks <greg.weeks@timesys.com>
Subject: Re: memcpy prefetch
From: Dominic Sweetman <dom@mips.com>
Date: Thu, 7 Apr 2005 13:28:33 +0100
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <4255240E.4050701@timesys.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4253D67C.4010705@timesys.com> <20050406200848.GB4978@linux-mips.org> <4255240E.4050701@timesys.com>
Sender: linux-mips-bounce@linux-mips.org
Greg Weeks (greg.weeks@timesys.com) writes:

> What's the performance hit for doing a pref on a cache line that is 
> already pref'd? Does it turn into a nop, or do we get some horrible 
> degenerate case?

The specification for the prefetch instruction is fairly wide, to
permit different implementations to act differently.  It's perfectly
legal for it to be a no-op.  However, implementors are told that they
should not do anything which would make performance *worse* than if it
was a no-op.

> Are 64 bit processors always at least 32 byte cache line size?

There's no reliable correlation.  If you were to go round the
"autogenerated at kernel-startup-time" route, then you can figure out
the line size from the "Config" registers (MIPS32- or MIPS64-compliant
CPUs) or from a table of CPU IDs or otherwise (earlier CPUs)...

--
Dominic Sweetman
MIPS Technologies

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