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Re: [PATCH] Using JR instead of J instruction for jumping to IRQ handler

To: "Nori, Soma Sekhar" <nsekhar@ti.com>
Subject: Re: [PATCH] Using JR instead of J instruction for jumping to IRQ handler.
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Sun, 13 Feb 2005 05:54:37 +0000 (GMT)
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
In-reply-to: <F6B01C6242515443BB6E5DDD63AE935F046834@dbde2k01.itg.ti.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <F6B01C6242515443BB6E5DDD63AE935F046834@dbde2k01.itg.ti.com>
Sender: linux-mips-bounce@linux-mips.org
On Sat, 12 Feb 2005, Nori, Soma Sekhar wrote:

> Attached patch attempts to use load address k0, <handler> followed by
> jump register k0 to jump to the MIPS IRQ handler from CAC_BASE + 0x200
> instead of just jump <handler>. This will enable jumping even if IRQ
> handler is linked at high kernel logical address. (like 0x94000000+).
> 
> I have tested this to work fine on my 4kec. (Not sure if the code will
> hold good for MIPS64 though)

 Well, it's where it would actually be especially useful, specifically for 
64-bit kernels loaded at XPHYS addresses.  Given it's generated code and 
this way of handling interrupts aims at improving performance (otherwise 
why bother using a separate vector at all?), it should actually determine 
whether an absolute jump suffices and emit code appropriately.

 That said, with the 4KEc you'd probably be better with using the CP0 
Ebase register instead.

  Maciej

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