| To: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
|---|---|
| Subject: | Re: c-r4k.c cleanup |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Mon, 7 Feb 2005 21:36:48 +0000 |
| Cc: | nigel@mips.com, linux-mips@linux-mips.org |
| In-reply-to: | <20050207.192450.55145246.nemoto@toshiba-tops.co.jp> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20050204.231254.74753794.anemo@mba.ocn.ne.jp> <4203890B.5030305@mips.com> <20050204145803.GA5618@linux-mips.org> <20050207.192450.55145246.nemoto@toshiba-tops.co.jp> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Mon, Feb 07, 2005 at 07:24:50PM +0900, Atsushi Nemoto wrote: > >>>>> On Fri, 4 Feb 2005 15:58:03 +0100, Ralf Baechle <ralf@linux-mips.org> > >>>>> said: > ralf> That's not a new feature in the MIPS world; the R10000 family > ralf> introduced that first and Linux knows how to make use of it. So > ralf> now I just need to teach c-r4k.c to check the AR bit on the 24K. > > 20KC Users Manual says it has physically indexed data cache. Correct - and just to make this CPU one of a rare breed in the MIPS world it also has virtually indexed, virtually tagged caches, similar to the Sibyte SB1. Sibyte still uses it's own cache code but eventually that should go away, so I've listed it also. Ralf |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: Strace doesn't work on linux-2.4.28 and later, Ralf Baechle |
|---|---|
| Next by Date: | Re: c-r4k.c cleanup, Ralf Baechle |
| Previous by Thread: | Re: c-r4k.c cleanup, Ralf Baechle |
| Next by Thread: | patch like kexec for MIPS possible?, Robert Michel |
| Indexes: | [Date] [Thread] [Top] [All Lists] |