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Re: c-r4k.c cleanup

To: linux-mips@linux-mips.org
Subject: Re: c-r4k.c cleanup
From: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Date: Mon, 7 Feb 2005 23:04:11 +0900
In-reply-to: <20050207213227.29f2d89b.yuasa@hh.iij4u.or.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050204.231254.74753794.anemo@mba.ocn.ne.jp> <4203890B.5030305@mips.com> <20050204145803.GA5618@linux-mips.org> <20050207.192450.55145246.nemoto@toshiba-tops.co.jp> <20050207213227.29f2d89b.yuasa@hh.iij4u.or.jp>
Sender: linux-mips-bounce@linux-mips.org
On Mon, 7 Feb 2005 21:32:27 +0900
Yoichi Yuasa <yuasa@hh.iij4u.or.jp> wrote:

> On Mon, 07 Feb 2005 19:24:50 +0900 (JST)
> Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> 
> > >>>>> On Fri, 4 Feb 2005 15:58:03 +0100, Ralf Baechle <ralf@linux-mips.org> 
> > >>>>> said:
> > ralf> That's not a new feature in the MIPS world; the R10000 family
> > ralf> introduced that first and Linux knows how to make use of it.  So
> > ralf> now I just need to teach c-r4k.c to check the AR bit on the 24K.
> > 
> > 20KC Users Manual says it has physically indexed data cache.
> > 
> > --- linux-mips.org/arch/mips/mm/c-r4k.c     2005-02-07 19:06:54.598390493 
> > +0900
> > +++ linux-mips/arch/mips/mm/c-r4k.c 2005-02-07 19:10:38.779771207 +0900
> > @@ -1016,6 +1016,8 @@
> >     case CPU_R10000:
> >     case CPU_R12000:
> >             break;
> > +   case CPU_20KC:  /* physically indexed */
> > +           break;
> >     case CPU_24K:
> >             if (!(read_c0_config7() & (1 << 16)))
> >     default:
> > 
> > For other MIPS64 core, 5Kc has virtually indexed cache.  How about 25KF?
> 
> 25Kf also has virtually indexed cache.

Sorry, D-cahce is physically indexed cache.

Yoichi

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