linux-mips
[Top] [All Lists]

Re: c-r4k.c cleanup

To: ralf@linux-mips.org
Subject: Re: c-r4k.c cleanup
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Mon, 07 Feb 2005 19:24:50 +0900 (JST)
Cc: nigel@mips.com, linux-mips@linux-mips.org
In-reply-to: <20050204145803.GA5618@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20050204.231254.74753794.anemo@mba.ocn.ne.jp> <4203890B.5030305@mips.com> <20050204145803.GA5618@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Fri, 4 Feb 2005 15:58:03 +0100, Ralf Baechle <ralf@linux-mips.org> 
>>>>> said:
ralf> That's not a new feature in the MIPS world; the R10000 family
ralf> introduced that first and Linux knows how to make use of it.  So
ralf> now I just need to teach c-r4k.c to check the AR bit on the 24K.

20KC Users Manual says it has physically indexed data cache.

--- linux-mips.org/arch/mips/mm/c-r4k.c 2005-02-07 19:06:54.598390493 +0900
+++ linux-mips/arch/mips/mm/c-r4k.c     2005-02-07 19:10:38.779771207 +0900
@@ -1016,6 +1016,8 @@
        case CPU_R10000:
        case CPU_R12000:
                break;
+       case CPU_20KC:  /* physically indexed */
+               break;
        case CPU_24K:
                if (!(read_c0_config7() & (1 << 16)))
        default:

For other MIPS64 core, 5Kc has virtually indexed cache.  How about 25KF?

---
Atsushi Nemoto

<Prev in Thread] Current Thread [Next in Thread>