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Re: c-r4k.c cleanup

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: c-r4k.c cleanup
From: Jun Sun <jsun@junsun.net>
Date: Fri, 4 Feb 2005 09:49:27 -0800
Cc: Dominic Sweetman <dom@mips.com>, Nigel Stephens <nigel@mips.com>, Atsushi Nemoto <anemo@mba.ocn.ne.jp>, linux-mips@linux-mips.org
In-reply-to: <20050204154532.GA22217@linux-mips.org>
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References: <20050204.231254.74753794.anemo@mba.ocn.ne.jp> <4203890B.5030305@mips.com> <20050204145803.GA5618@linux-mips.org> <16899.37525.412441.558873@gargle.gargle.HOWL> <20050204154532.GA22217@linux-mips.org>
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On Fri, Feb 04, 2005 at 04:45:32PM +0100, Ralf Baechle wrote:
> On Fri, Feb 04, 2005 at 03:19:49PM +0000, Dominic Sweetman wrote:
> 
> > Only some CPUs suffer from aliases.  A 4Kbyte direct-mapped cache must
> > be alias free, because all the virtual index bits are the same (being
> > in-page) as the physical address bits.  That's true but irrelvant,
> > since there aren't any 4Kbyte caches: but what's slightly less obvious
> > is that a 16Kbyte 4-way set-associative cache is also alias free.
> 
> I had dark memory of some el cheapo CPU having 4k caches.
> 

IDT (rc32332) has a 2K d-cache. :)

Jun

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