Fix some (maybe) missing syncs in bitops.h

[Daniel Jacobowitz <dan@debian.org>]

If I'm reading the broadcom documentation right, the semantics of set_bit
and test_and_set_bit require a sync at the end on this architecture.

I've been trying to track down a nasty signal delivery bug that I thought
was a TIF_SIGPENDING not being visible on the other CPU early enough.  Turns
out that wasn't the problem, but I still think the syncs are correct, so I'm
posting the patch.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>

Index: linux/include/asm-mips/bitops.h
===================================================================
--- linux.orig/include/asm-mips/bitops.h        2005-01-20 16:31:45.921742674 
-0500
+++ linux/include/asm-mips/bitops.h     2005-01-20 19:56:37.420056584 -0500
@@ -34,6 +34,7 @@
 #include <asm/interrupt.h>
 #include <asm/sgidefs.h>
 #include <asm/war.h>
+#include <asm/system.h>
 
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
@@ -76,6 +77,9 @@
                "       or      %0, %2                                  \n"
                "       "__SC   "%0, %1                                 \n"
                "       beqzl   %0, 1b                                  \n"
+#ifdef CONFIG_SMP
+               "sync                                                   \n"
+#endif
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else if (cpu_has_llsc) {
@@ -84,6 +88,9 @@
                "       or      %0, %2                                  \n"
                "       "__SC   "%0, %1                                 \n"
                "       beqz    %0, 1b                                  \n"
+#ifdef CONFIG_SMP
+               "sync                                                   \n"
+#endif
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else {
@@ -195,6 +204,9 @@
                "       xor     %0, %2                          \n"
                "       "__SC   "%0, %1                         \n"
                "       beqzl   %0, 1b                          \n"
+#ifdef CONFIG_SMP
+               "sync                                           \n"
+#endif
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else if (cpu_has_llsc) {
@@ -206,6 +218,9 @@
                "       xor     %0, %2                          \n"
                "       "__SC   "%0, %1                         \n"
                "       beqz    %0, 1b                          \n"
+#ifdef CONFIG_SMP
+               "sync                                           \n"
+#endif
                : "=&r" (temp), "=m" (*m)
                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
        } else {


-- 
Daniel Jacobowitz