| To: | Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> |
|---|---|
| Subject: | Re: [PATCH] Further TLB handler optimizations |
| From: | Rojhalat Ibrahim <ibrahim@schenk.isar.de> |
| Date: | Tue, 11 Jan 2005 09:10:50 +0100 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20050110154246.GH15344@rembrandt.csv.ica.uni-stuttgart.de> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20041223202526.GA2254@deprecation.cyrius.com> <20041224040051.93587.qmail@web52806.mail.yahoo.com> <20041224085645.GJ3539@rembrandt.csv.ica.uni-stuttgart.de> <20050107190605.GG31335@rembrandt.csv.ica.uni-stuttgart.de> <41E27A6A.5060204@schenk.isar.de> <20050110140429.GC15344@rembrandt.csv.ica.uni-stuttgart.de> <41E29DF5.6040800@schenk.isar.de> <20050110154246.GH15344@rembrandt.csv.ica.uni-stuttgart.de> |
| Sender: | linux-mips-bounce@linux-mips.org |
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Thiemo Seufer wrote: This would be a different bug then. It should be relatively easy to catch, there aren't that many places where cpu_has_64bit_gp_regs is used. I see you already fixed it. Works fine now. Thanks a lot. Rojhalat Ibrahim |
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