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Re: [PATCH] Further TLB handler optimizations

To: Rojhalat Ibrahim <ibrahim@schenk.isar.de>
Subject: Re: [PATCH] Further TLB handler optimizations
From: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Date: Mon, 10 Jan 2005 15:35:35 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <20050110140429.GC15344@rembrandt.csv.ica.uni-stuttgart.de>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20041223202526.GA2254@deprecation.cyrius.com> <20041224040051.93587.qmail@web52806.mail.yahoo.com> <20041224085645.GJ3539@rembrandt.csv.ica.uni-stuttgart.de> <20050107190605.GG31335@rembrandt.csv.ica.uni-stuttgart.de> <41E27A6A.5060204@schenk.isar.de> <20050110140429.GC15344@rembrandt.csv.ica.uni-stuttgart.de>
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Thiemo Seufer wrote:
> Rojhalat Ibrahim wrote:
> > Thiemo Seufer wrote:
> > >
> > >I updated the patch now and checked it in. Please test, especially
> > >for cases I couldn't do, like R3000-style TLB handling and MIPS32
> > >CPUs with 64bit physaddr.
> > >
> > 
> > My Yosemite board (RM9000 processor) does not boot anymore with
> > CONFIG_64BIT_PHYS_ADDR. Without that option it seems to be working
> > as before. I tried to define cpu_has_64bit_gp_regs.
> 
> Correct, this should always be defined for 64bit capable CPUs.
> 
> > With that it boots partly.
> 
> Where does it fail?

It's probably caused by the bug I just found. Please try the appended
patch and tell me if it changes something for you.


Thiemo


Index: arch/mips/mm/tlbex.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/tlbex.c,v
retrieving revision 1.14
diff -u -p -r1.14 tlbex.c
--- arch/mips/mm/tlbex.c        8 Jan 2005 15:03:53 -0000       1.14
+++ arch/mips/mm/tlbex.c        10 Jan 2005 14:23:38 -0000
@@ -1324,8 +1324,9 @@ iPTE_SW(u32 **p, struct reloc **r, unsig
                /* no i_nop needed */
                i_lw(p, pte, 0, ptr);
        } else
-# else
                i_nop(p);
+# else
+       i_nop(p);
 # endif
 #else
 # ifdef CONFIG_64BIT_PHYS_ADDR

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