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Re: [PATCH] Further TLB handler optimizations

To: linux-mips@linux-mips.org
Subject: Re: [PATCH] Further TLB handler optimizations
From: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Date: Fri, 7 Jan 2005 20:06:05 +0100
In-reply-to: <20041224085645.GJ3539@rembrandt.csv.ica.uni-stuttgart.de>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20041223202526.GA2254@deprecation.cyrius.com> <20041224040051.93587.qmail@web52806.mail.yahoo.com> <20041224085645.GJ3539@rembrandt.csv.ica.uni-stuttgart.de>
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Thiemo Seufer wrote:
> Manish Lachwani wrote:
> > Hello !
> > 
> > In what way does it break? Can you please provide more
> > details. Also, does it break on UP or SMP?
> 
> Userland starts to fail for simple tasks like 'ls -la'. The test was
> done with 64bit SMP on a board which needs the m3 workaround. The
> current CVS version works.
> 
> I guess the failure is caused by some missing bits for the m3
> workaround which only show up for the optimized handlers in 64bit mode.

Actually, it was caused by a stupid bug. The label to restart
the TLB modification on concurrent SMP updates was defined twice,
meaning it failed to re-execute the first half.

This also means that current 32bit SMP kernels have an easily
observable race condition there.

I updated the patch now and checked it in. Please test, especially
for cases I couldn't do, like R3000-style TLB handling and MIPS32
CPUs with 64bit physaddr.


Thiemo

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