Re: [PATCH] Further TLB handler optimizations

[Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>]

Thiemo Seufer wrote:
> Manish Lachwani wrote:
> > Hello !
> > 
> > In what way does it break? Can you please provide more
> > details. Also, does it break on UP or SMP?
> 
> Userland starts to fail for simple tasks like 'ls -la'. The test was
> done with 64bit SMP on a board which needs the m3 workaround. The
> current CVS version works.
> 
> I guess the failure is caused by some missing bits for the m3
> workaround which only show up for the optimized handlers in 64bit mode.

Actually, it was caused by a stupid bug. The label to restart
the TLB modification on concurrent SMP updates was defined twice,
meaning it failed to re-execute the first half.

This also means that current 32bit SMP kernels have an easily
observable race condition there.

I updated the patch now and checked it in. Please test, especially
for cases I couldn't do, like R3000-style TLB handling and MIPS32
CPUs with 64bit physaddr.


Thiemo