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Re: Some cache questions

To: linux-mips@linux-mips.org
Subject: Re: Some cache questions
From: Thomas Petazzoni <thomas.petazzoni@enix.org>
Date: Tue, 28 Dec 2004 09:21:31 +0100
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Hello,

Manish Lachwani a écrit :

For chip revisions 1.0 and 1.1, there are some changes
to the memory management subsystem for the kernel to
work on the board (dual core). As already known, these
versions dont support Shared state.

I had made those changes to the 2.4.21 kernel. Maybe
you can take a look at those changes and port them to
2.6 appropriately. However, there is more sanity in
1.2 version

Actually, my question was not really Linux-specific. On the second core, I will not use the MMU, because this core will not run Linux, but a custom code. Both cores will share informations through KSEG0, so I need to maintain coherency between caches. What should I do in order to do that ? Is it enough to set cache mode for KSEG0 to 4 (in the CONFIG register) ?

I have only 1.0 and 1.1 cores, on home-made boards, so there's no way to switch to 1.2.

BTW, do you have pointers, papers, information about a system running Linux on a core, and some custom code on a second core, in order to have real-time on the second core with very low latency ?

Thanks,

Thomas
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