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RE: Some cache questions

To: "'Thomas Petazzoni'" <thomas.petazzoni@enix.org>, linux-mips@linux-mips.org
Subject: RE: Some cache questions
From: Brad Larson <Brad_Larson@pmc-sierra.com>
Date: Mon, 27 Dec 2004 14:11:15 -0800
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
You haven't mentioned which board.  If its Yosemite then you may have one of 
the few not upgraded to 1.2 silicon.  If so it won't work with the changes 
committed by Ralf which requires the shared state for SMP boot.  For further 
discussion contact the apps@pmc-sierra.com

--Brad

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Thomas Petazzoni
Sent: Monday, December 27, 2004 8:35 AM
To: linux-mips@linux-mips.org
Subject: Some cache questions


Hello,

I'm using an RM9000 dual-core processor, buggy revisions (the one that 
doesn't support the "Shared" cache state if I understood correctly).

When going through the CVS logs, I saw that Ralf quite recently changed 
the cache mode from 4 to 5 in pgtable-bits.h. Is that change involved in 
the use of the "Shared" cache state with newer RM9000 revisions that 
don't have the bug ?

Currently, the KSEG0 cache coherency mode (2 lower bits of the CONFIG 
register) is set to 3 during PMON (start.S file). When I write something 
to the memory through KSEG0 with the first core, it doesn't appear to be 
read by the second core. This indicates, in my opinion, that the cache 
line of the first core hasn't been written to memory so that the second 
core could use it. Am I right ?

If I want to correctly use both cores using KSEG0, should I set the mode 
in the CONFIG register to 4 (so that I can work with buggy processors) ?

Thanks,

Thomas
-- 
PETAZZONI Thomas - thomas.petazzoni@enix.org
http://thomas.enix.org - Jabber: thomas.petazzoni@jabber.dk
http://kos.enix.org, http://sos.enix.org
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