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Some cache questions

To: linux-mips@linux-mips.org
Subject: Some cache questions
From: Thomas Petazzoni <thomas.petazzoni@enix.org>
Date: Mon, 27 Dec 2004 17:35:07 +0100
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Hello,

I'm using an RM9000 dual-core processor, buggy revisions (the one that doesn't support the "Shared" cache state if I understood correctly).

When going through the CVS logs, I saw that Ralf quite recently changed the cache mode from 4 to 5 in pgtable-bits.h. Is that change involved in the use of the "Shared" cache state with newer RM9000 revisions that don't have the bug ?

Currently, the KSEG0 cache coherency mode (2 lower bits of the CONFIG register) is set to 3 during PMON (start.S file). When I write something to the memory through KSEG0 with the first core, it doesn't appear to be read by the second core. This indicates, in my opinion, that the cache line of the first core hasn't been written to memory so that the second core could use it. Am I right ?

If I want to correctly use both cores using KSEG0, should I set the mode in the CONFIG register to 4 (so that I can work with buggy processors) ?

Thanks,

Thomas
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PETAZZONI Thomas - thomas.petazzoni@enix.org
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