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Re: [PATCH 2.6] tlbwr hazard for NEC VR4100

To: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Subject: Re: [PATCH 2.6] tlbwr hazard for NEC VR4100
From: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Date: Thu, 2 Dec 2004 01:07:13 +0100
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips <linux-mips@linux-mips.org>
In-reply-to: <20041201234943.584d88e8.yuasa@hh.iij4u.or.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20041201234943.584d88e8.yuasa@hh.iij4u.or.jp>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.6i
Yoichi Yuasa wrote:
> Hi Ralf,
> 
> This patch had added tlbwr hazard for NEC VR4100.
> Please apply this patch to 2.6.
> 
> Yoichi
> 
> Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
> 
> diff -urN -X dontdiff a-orig/arch/mips/mm/tlbex.c a/arch/mips/mm/tlbex.c
> --- a-orig/arch/mips/mm/tlbex.c       Tue Nov 30 20:42:08 2004
> +++ a/arch/mips/mm/tlbex.c    Wed Dec  1 23:23:11 2004
> @@ -820,6 +820,25 @@
>               i_ssnop(p);
>               break;
>  
> +     case CPU_VR4111:
> +     case CPU_VR4121:
> +     case CPU_VR4122:
> +     case CPU_VR4181:
> +     case CPU_VR4181A:
> +             i_nop(p);
> +             i_nop(p);
> +             i_tlbwr(p);
> +             i_nop(p);
> +             i_nop(p);
> +             break;
> +
> +     case CPU_VR4131:
> +     case CPU_VR4133:
> +             i_nop(p);
> +             i_nop(p);
> +             i_tlbwr(p);
> +             break;

If 64bit kernels are ever relevant for VR41xx, you might want to use
the same branch trick as it is used for R4[04]00. IIRC it reduced the
handler size from 34 to 30 instructions, saving another branch.

(If the XTLB refill handler doesn't fit in 32 instructions, it wraps
around to the 32bit TLB handler space and continues there. This costs
1-3 additional instructions.)


Thiemo

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