|To:||Gilad Rom <email@example.com>|
|Subject:||Re: CP0 EntryLo|
|From:||Pete Popov <firstname.lastname@example.org>|
|Date:||Tue, 30 Nov 2004 10:45:23 -0800|
|Cc:||"'Maciej W. Rozycki'" <email@example.com>, firstname.lastname@example.org|
|User-agent:||Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.3) Gecko/20040913|
Okay. I've pretty much figured out that part. What I'm puzzled About now is how do change the values of the CP0 EntryLo0/1 Registers, since I've changed the DTY bits to "1" on the MEM_STCFG1Register (in order to set it to work in "I/O Device" mode) , I need to "change bits 29:26 of CoProcessor 0 to 0xD" (Au1500 Databookquote) since the Databook doesn't specify an offset To these registers, I assume they're not like the other Registers I've been dealing with (Chip Select and GPIO).
The reason for the 0XD is because the CS is on a 36 bit physical address. You're in luck because the 36 bit address support went in the 2.6 tree a couple of days ago (I don't remember if you're using 2.4 or 2.6, but 2.4 has the 36 bit support as well). You don't mess with the tlb registers yourself -- you let ioremap do its work. Take a look at drivers/pcmcia/au1000_generic.c and you'll see how the pcmcia CS is remapped. You simply pass the 36 bit phys address and ioremap will do its job.
If there was no 36 bit address support in the kernel, your only option would have been to use a wired tlb, and then you would end up programming the tlb registers directly. In this case there is no reason to do that because ioremap will handle the 36 bit phys address.
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