Re: Cache Question

[Ralf Baechle <ralf@linux-mips.org>]

On Wed, Nov 24, 2004 at 10:42:45PM +0000, Maciej W. Rozycki wrote:

> > That interrupt disabling in some cache flushes dates back further than
> > CVS history.  Seems once uppon a time there was some CPU which didn't
> > like cache flushes with interrupts enabled.  This is rather bad for
> > latencies so unless somebody else on this list recalls a good reason
> > I'd like to remove this.
> 
>  Some R4600 (v1.1?) errata workaround?  Or was it elsewhere?

V1.7 you mean - it identifies as 1.0 in c0_prid though.  I don't have
my erratas for this one anymore.  I've checked erratum #3 of V2.0 with
one of the R4600 designers already a while ago and he said disabling
interrupts isn't necessary.

The ancient Linux code I was refering to used to disable interrupts
for all CPUs.  Supported CPUs back then were R4000, R4400, R4600 only,
so it must have been one of those.

  Ralf