| To: | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Subject: | Re: Cache Question |
| From: | "Maciej W. Rozycki" <macro@linux-mips.org> |
| Date: | Wed, 24 Nov 2004 22:42:45 +0000 (GMT) |
| Cc: | "Kapoor, Pankaj" <pkapoor@ti.com>, linux-mips@linux-mips.org |
| In-reply-to: | <20041124223211.GB22439@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <C4D23DECD6CD714BBFB38B0AE8D25A3A24FF66@dlee2k03.ent.ti.com> <20041124223211.GB22439@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Wed, 24 Nov 2004, Ralf Baechle wrote: > That interrupt disabling in some cache flushes dates back further than > CVS history. Seems once uppon a time there was some CPU which didn't > like cache flushes with interrupts enabled. This is rather bad for > latencies so unless somebody else on this list recalls a good reason > I'd like to remove this. Some R4600 (v1.1?) errata workaround? Or was it elsewhere? Maciej |
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