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Re: Cache Question

To: "Kapoor, Pankaj" <pkapoor@ti.com>
Subject: Re: Cache Question
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 24 Nov 2004 23:32:12 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <C4D23DECD6CD714BBFB38B0AE8D25A3A24FF66@dlee2k03.ent.ti.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <C4D23DECD6CD714BBFB38B0AE8D25A3A24FF66@dlee2k03.ent.ti.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.1i
On Tue, Nov 23, 2004 at 12:19:21PM -0600, Kapoor, Pankaj wrote:

> Is there any specific reason why the cache invalidation routine is
> executed with interrupts disabled? 

That interrupt disabling in some cache flushes dates back further than
CVS history.  Seems once uppon a time there was some CPU which didn't
like cache flushes with interrupts enabled.  This is rather bad for
latencies so unless somebody else on this list recalls a good reason
I'd like to remove this.

  Ralf

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