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Re: [PATCH] Synthesize TLB refill handler at runtime

To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Subject: Re: [PATCH] Synthesize TLB refill handler at runtime
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 24 Nov 2004 10:44:23 +0100
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, Manish Lachwani <mlachwani@mvista.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Linux/MIPS Development <linux-mips@linux-mips.org>
In-reply-to: <20041124014057.GE902@rembrandt.csv.ica.uni-stuttgart.de>
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References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> <Pine.GSO.4.61.0411212048520.26374@waterleaf.sonytel.be> <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> <20041122070117.GB25433@linux-mips.org> <41A283BD.3080300@mvista.com> <Pine.LNX.4.58L.0411230036310.31113@blysk.ds.pg.gda.pl> <41A29DCF.8030308@mvista.com> <Pine.LNX.4.58L.0411232018390.19941@blysk.ds.pg.gda.pl> <20041124014057.GE902@rembrandt.csv.ica.uni-stuttgart.de>
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On Wed, Nov 24, 2004 at 02:40:57AM +0100, Thiemo Seufer wrote:

> >     default:
> >             /*
> >              * Others are assumed to have one cycle mtc0 hazard,
> > -            * and one cycle tlbwr hazard.
> > +            * and one cycle tlbwr hazard or to understand ehb.
> >              * XXX: This might be overly general.
> >              */
> > -           i_nop(p);
> > +           i_ehb(p);
> >             i_tlbwr(p);
> > -           i_nop(p);
> > +           i_ehb(p);
> >             break;
> 
> Does r24k really need both delays? If not, it should get its own case.
> Probably it should be separated even if it is identical, the code above
> is nothing but a guess based on preexisting code.

I would suggest to default to EHB only for architecture revision 2.  For
any pre-V2 processor the outcome of a default case is basically luck and
so I would suggest to just panic and force people to read their CPU
manual.

  Ralf

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