linux-mips
[Top] [All Lists]

[PATCH] Comments in the titan ethernet driver for IP header alignment

To: linux-mips@linux-mips.org
Subject: [PATCH] Comments in the titan ethernet driver for IP header alignment
From: Manish Lachwani <mlachwani@prometheus.mvista.com>
Date: Tue, 23 Nov 2004 09:14:21 -0800
Cc: ralf@linux-mips.org
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.1i
Hi Ralf,

Attached patch puts comments around the section that programs register 0x103C
for IP header alignment. Please review ...

Thanks
Manish Lachwani

--- drivers/net/titan_ge.c.orig 2004-11-23 09:00:29.000000000 -0800
+++ drivers/net/titan_ge.c      2004-11-23 09:12:07.000000000 -0800
@@ -1000,6 +1000,17 @@
         * driver. This performance drawback existed in the previous
         * versions of the silicon
         */
+       /*
+        * The register (0x103c) below has been used to program the 
+        * chip to do the IP header alignment. The idea was to fix the
+        * IP header alignment by using existing unused registers,
+        * so that this feature can be implemented quickly. If these 
+        * registers are not programmed, then the chip will not align the 
+        * IP headers and an extra copy would have to be implemented
+        * in the driver on the Rx side. I am not sure if this 
+        * has been documented.  
+        *                      - Manish Lachwani (11/23/2004)
+        */
        reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
        reg_data_1 |= 0x40000000;
        TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
<Prev in Thread] Current Thread [Next in Thread>