Ralf Baechle wrote:
On Thu, Nov 18, 2004 at 11:43:51PM +0100, TheNop wrote:
I use the chip version 1.1.
Now I have the problem, that I can not use the newest code, until 1.2
version of the chip is available.
Is it possible to make the code usable for all chip version by choosing
the version at the kernel configuration?
Titan 1.2 is available since quite a while - the dust on my board is
proof ;-) Since Titan 1.0 and 1.0 were shipped in very low numbers to
early customers only and will never be available in volume production the
support for them was removed. As I recall there were at least these
problems with Titan 1.0 and 1.1 in Linux:
- Linux uses the prefetch prepare for store operation.
- Coherency mode 5 which is mandatory for good performance and any kind
of sanity on SMP is now being used.
- The problem with the third ethernet port which Manish just had
You can dig through XCVS, WebCVS or the linux-cvs archive to find where
I broke backward compatibility.
Ralf, thanks for the good description. Anyways, just to make it a little
more clear. Port #2 (third ethernet port) was not working on Titan 1.0
and 1.1. This is because there is no interrupt line on which interrupts
for port #2 could be routed. And Titan MACs cannot share interrupts.
One other problem with 1.0 and 1.1 was that for incoming packets, the IP
header is not aligned. As a result, an extra copy was implemented in the
driver to align this IP header. This problem exists on all ports (0 and 1).
With Titan 1.2, there is no need for the extra copy and port #2 can be
enabled since there is an interrupt line which it can use.
And of course, 1.0 and 1.1 did not support the five state MOESI
protocol. They supported MEI only.