Re: [PATCH]PCI on SWARM

[Jes Sorensen <jes@wildopensource.com>]

>>>>> "Maciej" == Maciej W Rozycki <macro@linux-mips.org> writes:

Maciej> On Mon, 18 Oct 2004, Jes Sorensen wrote: 
>>  Dual address cycles, ie. 64 bit addressing is fscked on the 1250
>> from what I remember. Correct way to work around this is to stick
>> all physical memory outside the 32 bit space into ZONE_HIGHMEM -
>> had a patch for 2.4, but I lost it ages ago ;-(

Maciej>  The BCM1250A's PCI is obviously 32-bit only (the host bridge
Maciej> is explicitly documented not to support DACs), but you need to
Maciej> use 64-bit addressing to access the whole 4GB range -- the bus
Maciej> is decoded starting from 0xf800000000 and 0xf900000000, with a
Maciej> different byte lane swapping policy for each of these areas.
Maciej> For limited access for 32-bit software, you can use alternate
Maciej> mappings at 0x40000000 and 0x60000000, but they provide only
Maciej> 512MB of space each.

Yeah it seems to be documented, it's highly unfortunate that anybody
will release a chip which doesn't support DAC but will support memory
outside the 4GB range. I'd be highly embarrassed if I had done the
chip, but thats just me.

I think you are right about the HT part.

Cheers,
JEs