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Re: [PATCH]PCI on SWARM

To: Jes Sorensen <jes@wildopensource.com>
Subject: Re: [PATCH]PCI on SWARM
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Mon, 18 Oct 2004 21:17:43 +0100 (BST)
Cc: Ralf Baechle <ralf@linux-mips.org>, Manish Lachwani <mlachwani@mvista.com>, linux-mips@linux-mips.org
In-reply-to: <yq0zn2ks9em.fsf@jaguar.mkp.net>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <416DE31E.90509@mvista.com> <20041014191754.GB30516@linux-mips.org> <Pine.LNX.4.58L.0410142305380.25607@blysk.ds.pg.gda.pl> <416EFBAB.8050600@mvista.com> <Pine.LNX.4.58L.0410142327530.25607@blysk.ds.pg.gda.pl> <20041014225553.GA13597@linux-mips.org> <Pine.LNX.4.58L.0410150311370.25607@blysk.ds.pg.gda.pl> <yq0zn2ks9em.fsf@jaguar.mkp.net>
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On Mon, 18 Oct 2004, Jes Sorensen wrote:

> Maciej>  Tough.  Both the PCI memory and the PCI I/O spaces are mapped
> Maciej> in several areas, depending on the byte lane swapping policy
> Maciej> needed and whether 64-bit addressing is feasible or not.  We'd
> Maciej> need two areas for I/O and four for memory (plus another one
> Maciej> for the 40-bit HT address space).
> 
> Dual address cycles, ie. 64 bit addressing is fscked on the 1250 from
> what I remember. Correct way to work around this is to stick all
> physical memory outside the 32 bit space into ZONE_HIGHMEM - had a
> patch for 2.4, but I lost it ages ago ;-(

 The BCM1250A's PCI is obviously 32-bit only (the host bridge is
explicitly documented not to support DACs), but you need to use 64-bit
addressing to access the whole 4GB range -- the bus is decoded starting
from 0xf800000000 and 0xf900000000, with a different byte lane swapping
policy for each of these areas.  For limited access for 32-bit software,
you can use alternate mappings at 0x40000000 and 0x60000000, but they
provide only 512MB of space each.

 I don't think something like DACs exists for HT.

  Maciej

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