linux-mips
[Top] [All Lists]

Re: [PATCH]PCI on SWARM

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH]PCI on SWARM
From: Jes Sorensen <jes@wildopensource.com>
Date: 18 Oct 2004 04:44:17 -0400
Cc: Ralf Baechle <ralf@linux-mips.org>, Manish Lachwani <mlachwani@mvista.com>, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.58L.0410150311370.25607@blysk.ds.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <416DE31E.90509@mvista.com> <20041014191754.GB30516@linux-mips.org> <Pine.LNX.4.58L.0410142305380.25607@blysk.ds.pg.gda.pl> <416EFBAB.8050600@mvista.com> <Pine.LNX.4.58L.0410142327530.25607@blysk.ds.pg.gda.pl> <20041014225553.GA13597@linux-mips.org> <Pine.LNX.4.58L.0410150311370.25607@blysk.ds.pg.gda.pl>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.3
>>>>> "Maciej" == Maciej W Rozycki <macro@linux-mips.org> writes:

Maciej> On Fri, 15 Oct 2004, Ralf Baechle wrote:
>> Sure, go ahead.  This btw should match with the pci_controller
>> definition which is looking fishy also.

Maciej>  Tough.  Both the PCI memory and the PCI I/O spaces are mapped
Maciej> in several areas, depending on the byte lane swapping policy
Maciej> needed and whether 64-bit addressing is feasible or not.  We'd
Maciej> need two areas for I/O and four for memory (plus another one
Maciej> for the 40-bit HT address space).

Dual address cycles, ie. 64 bit addressing is fscked on the 1250 from
what I remember. Correct way to work around this is to stick all
physical memory outside the 32 bit space into ZONE_HIGHMEM - had a
patch for 2.4, but I lost it ages ago ;-(

One can just hope Broadcom will learn how to make chips some day ;-(

Regards,
Jes

<Prev in Thread] Current Thread [Next in Thread>