| To: | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Subject: | Re: [PATCH]PCI on SWARM |
| From: | "Maciej W. Rozycki" <macro@linux-mips.org> |
| Date: | Fri, 15 Oct 2004 03:19:55 +0100 (BST) |
| Cc: | Manish Lachwani <mlachwani@mvista.com>, linux-mips@linux-mips.org |
| In-reply-to: | <20041014225553.GA13597@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <416DE31E.90509@mvista.com> <20041014191754.GB30516@linux-mips.org> <Pine.LNX.4.58L.0410142305380.25607@blysk.ds.pg.gda.pl> <416EFBAB.8050600@mvista.com> <Pine.LNX.4.58L.0410142327530.25607@blysk.ds.pg.gda.pl> <20041014225553.GA13597@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Fri, 15 Oct 2004, Ralf Baechle wrote: > Sure, go ahead. This btw should match with the pci_controller definition > which is looking fishy also. Tough. Both the PCI memory and the PCI I/O spaces are mapped in several areas, depending on the byte lane swapping policy needed and whether 64-bit addressing is feasible or not. We'd need two areas for I/O and four for memory (plus another one for the 40-bit HT address space). Maciej |
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