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Re: PATCH

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: PATCH
From: Pete Popov <ppopov@embeddedalley.com>
Date: Sun, 10 Oct 2004 15:50:14 -0700
Cc: Geert Uytterhoeven <geert@linux-m68k.org>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
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Maciej W. Rozycki wrote:
On Sun, 10 Oct 2004, Geert Uytterhoeven wrote:


Ralf, or anyone else, any suggestions on how to get a patch like the one
below accepted in 2.6? It's needed due to the 36 bit address of the
pcmcia controller on the Au1x CPUs.

Perhaps you can ask the PPC people? Book E PPC has 36-bit I/O as well.


 Using 36-bit pointers for PCMCIA seems questionable to me -- does the bus
support such wide addresses?

Sort of. The internal CPU bus has a 36 bit chip select. You never see the 36 bit phys address on the bus, but the PCI, external LCD, and pcmcia addresses are 36 bit. That's the reason for the 36 bit I/O address patch I sent last night.

If not, why not use a data type that covers
valid offsets only when passing addresses to bus access functions?

The attribute and memory pcmcia addresses are just stored in these variables, and then the upper pcmcia stack layer calls ioremap on these addresses. Thus, you need the 36 bit I/O address patch, as well as the tiny pcmcia patch.

The pcmcia I/O address is ioremapped at the socket driver level. If that was the case with the mem and attribute addresses, I wouldn't need this 64 bit pcmcia patch. But since it's the upper pcmcia layer that ioremaps these addresses, I need to store tham in 64 bit types.

Pete

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