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RE: ...cache dimensioning ;-)

To: Adrian Hulse <adrian.hulse@lantronix.com>
Subject: RE: ...cache dimensioning ;-)
From: Emmanuel Michon <em@realmagic.fr>
Date: Sat, 11 Sep 2004 16:58:17 +0200
Cc: linux-mips@linux-mips.org
In-reply-to: <2F0FC2A92C0B154BB406D5E74CB3E6930B7EAC@3putt.int.lantronix.com>
Organization: REALmagic France SAS
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <2F0FC2A92C0B154BB406D5E74CB3E6930B7EAC@3putt.int.lantronix.com>
Sender: linux-mips-bounce@linux-mips.org
On Fri, 2004-09-10 at 20:41, Adrian Hulse wrote:
> >If I consider a platform like Toshiba TX39 which has d-cache four ways
> >with total 32KBytes, it must already have the problems above. I'd like
> >to get some more clues though...
> 
> You probably meant to say Tx49 no ? The Tx39 has 16/8 k Instruction
> Cache, 8/4 k Data cache.

Sorry, yes, TX4938 (so far I could not boot linux from linux-mips cvs
tag 2_4_26 on this (I chose TX49[23]7 platform))

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