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RE: ...cache dimensioning ;-)

To: "Emmanuel Michon" <em@realmagic.fr>, <linux-mips@linux-mips.org>
Subject: RE: ...cache dimensioning ;-)
From: "Adrian Hulse" <adrian.hulse@lantronix.com>
Date: Fri, 10 Sep 2004 11:41:12 -0700
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Thread-index: AcSXH00BrWq+afm6TKCskpGI20ie5wARhLYQ
Thread-topic: ...cache dimensioning ;-)
>If I consider a platform like Toshiba TX39 which has d-cache four ways
>with total 32KBytes, it must already have the problems above. I'd like
>to get some more clues though...

You probably meant to say Tx49 no ? The Tx39 has 16/8 k Instruction
Cache, 8/4 k Data cache.



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