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Re: TLB dimensioning

To: Dominic Sweetman <dom@mips.com>
Subject: Re: TLB dimensioning
From: Johannes Stezenbach <js@convergence.de>
Date: Thu, 2 Sep 2004 12:19:57 +0200
Cc: Emmanuel Michon <em@realmagic.fr>, linux-mips@linux-mips.org
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Dominic Sweetman wrote:
> 
> Emmanuel,
> 
> > regarding the hardware implementation of a 4KE (r4k style mmu
> > if I remember) I'm wondering about the performance difference
> > when the TLB has 16 pairs of entries (covering 128KBytes of
> > data) or 32 pairs (covering 256KBytes).
> > 
> > Does someone have a useful advise regarding the `nice spot'
> > for TLB size?
...
> However, the measurements we've done at MIPS suggest that for
> moderate-size workloads where the user-space programs are working
> hard, a 16-entry TLB can thrash quite badly, making a significant dent
> in performance.
> 
> So the advice I'd give is that if:
> 
> 1. Your application has a non-trivial user space of any size;
> 
> 2. The performance of userland code is significant;
> 
> then you should pick a 32-entry TLB, until and unless you have
> measurements of your own application to show you don't need it.

Hm, the MIPS32 4K Processor Core Family Software User's Manual says:

"...the 4Kc core contains a 3-entry instruction TLB (ITLB), a 3-entry
data TLB(DTLB), and a 16 dual-entry joint TLB (JTLB) with variable page
sizes."

What exactly does that mean, and how does it rate performancewise?
I'm just curious ;-)

Johannes

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