|To:||Jun Sun <email@example.com>|
|Subject:||Re: do_ri failure in cache flushing routines|
|From:||G H <firstname.lastname@example.org>|
|Date:||Thu, 5 Aug 2004 13:25:30 -0700 (PDT)|
I was also thinking that maybe it could be related to the MIPS32 instruction cache flushing routine, so I tried applying the patch Ralf posted. The system still functioned OK for me, but one other in my group had their board lock up hard ( no oops produced ), and when I asked Ralf if that patch was ready for applying to CVS, he said it needed to be reworked before doing that. As a result we didn't follow up too closely on that avenue of investigation.
So basically what I am concluding from the responses so far , is that do_ri should NEVER occur in blast_icache32() and for it to do so, it could be either a hardware problem, or possibly the MIPS32 icache flushing problem.
Anyone agree / disagree ?
Jun Sun <email@example.com> wrote:
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