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Re: do_ri failure in cache flushing routines

To: G H <giles67@yahoo.com>
Subject: Re: do_ri failure in cache flushing routines
From: Jun Sun <jsun@mvista.com>
Date: Thu, 5 Aug 2004 11:11:33 -0700
Cc: linux-mips@linux-mips.org, jsun@mvista.com
In-reply-to: <20040805180427.59029.qmail@web50806.mail.yahoo.com>; from giles67@yahoo.com on Thu, Aug 05, 2004 at 11:04:27AM -0700
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On Thu, Aug 05, 2004 at 11:04:27AM -0700, G H wrote:
> I've not had much response to this question so I would like to rephrase it :
>  
> Can anyone think of any possible scenario where do_ri could occur in 
> blast_icache32() ??
>  

One possibility _could_ be the "instruction flushing itself" problem on
MIPS32.  However, as far as I know au1x00 CPUs don't suffer from this problem.
Anybody knows for sure?

You could try to use the two phase cache flushing (such as the one used
by tx47xx and also see an earlier related discussion thread) and see if
the problem goes away.

Jun

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