| To: | linux-mips@linux-mips.org |
|---|---|
| Subject: | RE: do_ri failure in cache flushing routines |
| From: | G H <giles67@yahoo.com> |
| Date: | Thu, 5 Aug 2004 11:04:27 -0700 (PDT) |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
|
I've not had much response to this question so I would like to rephrase it :
Can anyone think of any possible scenario where do_ri could occur in blast_icache32() ??
Is this possibly a cache synchronisation problem ??
TIA
>While testing out an amd au1500 based board I have been getting " do_ri " exceptions >that always occur in the cache flushing routines. More often than not in >blast_icache_32().
>So far this has mainly happened after running the board for days on end while running >multiple telnet sessions to it. It has sometimes ( quite rarely ) happened after a few >hours to a day of multiple telnet session use. __________________________________________________ |
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