linux-mips
[Top] [All Lists]

RM9000x2 TLB load exception

To: linux-mips@linux-mips.org
Subject: RM9000x2 TLB load exception
From: willem.acke@alcatel.be
Date: Mon, 02 Aug 2004 11:19:27 +0200
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.5) Gecko/20031007
All,

I'm trying to port the mips-kernel to a RM9000x2 based custom board.
The kernel file (mips 32) is loaded using VxWorks boot loader.
I got the to the point where the kernel starts loading, but exits with a 'TLB load exception'. After putting in a number of printks, it seems that it fails on 'flush_icache_range' in arch/mips/mm/pg-r4k.c -> build_clear_page. Since I'm a newbie to this, any pointers to how to tackle this problem would be appreciated.

Exception:
Tlb Load Exception
Exception Program Counter: 0x00000000
Status Register: 0x3404ff00
Cause Register: 0x01100008
Access Address : 0x00000000
Task: 0x83e2c760 ""

$0 = 0 t0 = 3ffffff s0 = 24810e00 at = 3404ff00 t1 = fffffffffc1fffff s1 = ffffffffac800000 v0 = 0 t2 = ffffffffffff0000 s2 = ffffffffac800004 v1 = 1 t3 = 800000 s3 = ffffffffcc9e0200 a0 = ffffffff801a6f30 t4 = ffffffffac000000 s4 = ffffffffac800008 a1 = ffffffff801a6f94 t5 = 40000 s5 = ffffffffac80000c a2 = ffffffff801508e8 t6 = 7fff s6 = 0 a3 = ffffffff80173e84 t7 = 24000000 s7 = 24840020
s8    = ffffffff83e2c268   k0    =                0
gp = ffffffff80172000 k1 = 0 t8 = a ra = ffffffff80179254 sp = ffffffff80173e80 t9 = ffffffffac80fff8
divlo =             1000   divhi =                0   sr    = 3404ff00
pc    =        0

Thanks in advance,

Wim Acke


<Prev in Thread] Current Thread [Next in Thread>