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Re: Strange, strange occurence

To: dom@mips.com
Subject: Re: Strange, strange occurence
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 15 Jul 2004 10:34:44 +0900 (JST)
Cc: ralf@linux-mips.org, KevinK@mips.com, theansweriz42@hotmail.com, linux-mips@linux-mips.org
In-reply-to: <16629.24775.778491.754688@arsenal.mips.com>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <00ba01c46823$3729b200$0deca8c0@Ulysses> <20040713003317.GA26715@linux-mips.org> <16629.24775.778491.754688@arsenal.mips.com>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Wed, 14 Jul 2004 17:35:19 +0100, Dominic Sweetman <dom@mips.com> said:
dom> 2. Arrange to skip those indexes when zapping the cache, then do
dom> something weird to invalidate that handful of lines.  You could
dom> do that by running uncached, but you could also do it just by
dom> using some auxiliary routine which is known to be more than a
dom> cache line but much less than a whole I-cache span distant, so
dom> can't possibly alias to the same thing...

dom> This is fiddly, but not terribly difficult and should have a
dom> negligible performance impact.

Yes.  The cache routines for TX49XX surely do it (2 phase
invalidating).  Please look at tx49_blast_icache32() in c-r4k.c.

---
Atsushi Nemoto

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