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Re: Strange, strange occurence

To: "Kevin D. Kissell" <KevinK@mips.com>
Subject: Re: Strange, strange occurence
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 13 Jul 2004 01:13:59 +0200
Cc: S C <theansweriz42@hotmail.com>, linux-mips@linux-mips.org
In-reply-to: <021201c4685f$2925ee30$0deca8c0@Ulysses>
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References: <BAY2-F27mxl2RtYP35u0000d191@hotmail.com> <020201c46859$fa6b98b0$0deca8c0@Ulysses> <021201c4685f$2925ee30$0deca8c0@Ulysses>
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On Tue, Jul 13, 2004 at 12:25:37AM +0200, Kevin D. Kissell wrote:

> Hmm.  On closer examination, there *is* a bug in the current 
> r4k_flush_icache_range(),
> in that it computes its cache flush loop for the I-cache based on the D-cache 
> line size.
> Those line sizes are *usually* the same.  By any chance are they different 
> for the
> TX49 family?  If the icache line is longer than the dcache line, there should 
> be no
> functional problem, just some wasted cycles.  But if the dcache line were, 
> say, 
> twice the length of the Icache line, only half of the icache lines would be 
> invalidated...

Whoops.  Fixing ...

  Ralf

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