Hi Kevin and Ralf,
Thanks for your inputs and suggestions! In the case of the Tx49 family, the
primary I and D cache lines are both the same size (8 words), so the problem
you mention below will not arise.
I didn't think about the meaning of cpu_has_ic_fills_f_dc before writing
my previous mail, and I see now that my intuition (and your explanation
helps) was correct.
For the moment, the problem is fixed. But I'm going to try and get to the
bottom of this when I have the time.
From: "Kevin D. Kissell" <KevinK@mips.com>
To: "Kevin D. Kissell" <KevinK@mips.com>, "S C"
<email@example.com>, "Ralf Baechle" <firstname.lastname@example.org>
Subject: Re: Strange, strange occurence
Date: Tue, 13 Jul 2004 00:25:37 +0200
> Your intuition is correct, and the code in r4k_tlb_init() does look
> But at least in the linux-mips CVS tree, flush_icache_range() tests to
> if "cpu_has_ic_fills_f_dc" (CPU has Icache fills from Dcache, I presume)
> is set, and if it isn't, it pushes the specified range out of the Dcache
> flushing the Icache. I would speculate that either your c-r4k.c is out
> sync with yout tlb-r4k.c, or you erroneously have cpu_has_ic_fills_f_dc
Hmm. On closer examination, there *is* a bug in the current
in that it computes its cache flush loop for the I-cache based on the
D-cache line size.
Those line sizes are *usually* the same. By any chance are they different
TX49 family? If the icache line is longer than the dcache line, there
should be no
functional problem, just some wasted cycles. But if the dcache line were,
twice the length of the Icache line, only half of the icache lines would be
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