| To: | Adam Kiepul <Adam_Kiepul@pmc-sierra.com> |
|---|---|
| Subject: | Re: [SiByte] RE: weird sb1250 behavior |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Fri, 28 May 2004 22:59:23 +0200 |
| Cc: | "'hadi@cyberus.ca'" <hadi@cyberus.ca>, linux-mips@linux-mips.org, sibyte-users@bitmover.com |
| In-reply-to: | <9DFF23E1E33391449FDC324526D1F2590283C58B@sjc1exm02.pmc_nt.nt.pmc-sierra.bc.ca> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <9DFF23E1E33391449FDC324526D1F2590283C58B@sjc1exm02.pmc_nt.nt.pmc-sierra.bc.ca> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Fri, May 28, 2004 at 01:11:38PM -0700, Adam Kiepul wrote:
> There is a possible cache line read-after-write pseudo-dependency that, along
> with the code alignment in terms of the instruction pair doublewords, may do
> something weird to the sb1250 pipeline. Just my guess.
memcpy's source deals with what probably is another instance of the same
effect:
#ifdef CONFIG_CPU_SB1
nop # improves slotting
#endif
Ralf
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