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IOC3 interrupt management

To: linux-mips@linux-mips.org
Subject: IOC3 interrupt management
From: Stanislaw Skowronek <sskowron@ET.PUT.Poznan.PL>
Date: Tue, 11 May 2004 19:56:40 +0200 (MET DST)
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Well, there is a problem _again_. This time it's a purely conceptual one.

The IOC3 on Octanes (maybe on Onyx2es, too) controls the Ethernet, 
keyboard, mouse, serial and parallel ports and SGI alone knows what else.

It is also tied to (at least) two bridge interrupts. One is used solely
for Ethernet, and the other one is used for all the SuperIO stuff.

Well, I'm an educated man (when it comes to Octane internals, that is)
and I know that the first interrupt is 2 and the other is 4, and that they
map to IRQ10 and IRQ12, respectively. But how should the poor kernel know
about such arcanes? There is not a word in the IOC3 registers about this
weird connection so the PCI drivers don't know about it at all.

Now this is not a problem - I could simply assume that all IOC3s will have
another IRQ at irq_num+2. But, MENET of course is build of four IOC3s and
is definitely arranged in some other way. And what about the single IOC3
cards? Do they have the other IRQ at all, or don't they allow using
SuperIO?

This will all end in a kludge.

Stanislaw Skowronek

--<=>--
  "You're not as old as the trees, not as young as the leaves.
   Not as free as the breeze, not as open as the seas."



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