> The way that PCI interrupts work on IP27 is: A device's INTA pin is
> connected to the BRIDGE ASIC.
Only INTAs? Does each INTA of a device have a dedicated pin on the bridge
(I am not sure, but it seems so)?
> When a device's interrupt line is asserted, the bridge ASIC will store
> a value which consists of 0x100 | intnum into another register; the
> address of that other register can be configured per device in the
> BRIDGE chip. The value is usuall the xtalk address of another
> register in the HUB ASIC. For HUB the value 0x100 | intnum would mean
> to set bit intnum in the interrupt pending register.
OK, I figured that out from the IRIX headers. Apparently, HEART does it
the same way, only the register is at 0x80 and not 0x90.
> The BRIDGE chip can also be configured to send an interrupt clear
> packet if the PCI interrupt is deasserted again; it's a good idea to
> have this enabled since otherwise writing race-free interrupt handlers
> is a PITA. The HUB chip then asserts one of the CPU interrupt lines
> if a bit is set in the interrupt pending register and mask0/mask1
> register for the CPU.
It is very similar to the HEART, then. But I didn't know about clear
> For a single node system this could be slightly simplified - no idea if
> SGI did that for the HEART design. Anyway, in case of an Origin you'd
> have to chase the interrupt through the various stages of processing:
> - Interupt sent from the device?
Well, I don't know... Should I take out my logic analyzer?
> - Interrupt asserted at BRIDGE?
I don't know this, either.
> - Interrupt bit set in HUB chip?
Well, if anything is asserted at the bridge, all the following steps are
correctly executed. It's a problem around the IOC. Could you please tell
me, how are IOC packets transmitted? What is the relation of this to the
I have tried to run NFSRoot, but the machine sends no packets, even though
it believes firmly that it sends (i.e. no error messages).
> I hope that's somehow applicable to the IP30 ...
So do I :)