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Re: MC Parity Error

To: Dominic Sweetman <>
Subject: Re: MC Parity Error
From: "Maciej W. Rozycki" <>
Date: Fri, 23 Apr 2004 23:06:24 +0200 (CEST)
Cc: Ralf Baechle <>, Florian Lohoff <>,
In-reply-to: <>
Organization: Technical University of Gdansk
Original-recipient: rfc822;
References: <> <> <> <> <>
On Fri, 23 Apr 2004, Dominic Sweetman wrote:

> > > The KSU bits are meaningless.  On Indy like most other MIPS systems a
> > > bus error exception may be delayed.  So the generic solution requires
> > 
> >  I beg your pardon?  AFAIK, bus errors are documented to be reported
> > precisely...
> You're both right :-) Data errors like this on an R4x00 are reported
> as cache parity errors, and cache parity error exceptions are precise.
> There's also a signalling mechanism typically used for an invalid
> memory address, which generates a "bus error" exception, which is not
> precise.

 I refer to the situation, when SysCmd(5) is set in a response to a
processor read request.

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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