linux-mips
[Top] [All Lists]

Re: MC Parity Error

To: Dominic Sweetman <dom@mips.com>
Subject: Re: MC Parity Error
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 23 Apr 2004 23:06:24 +0200 (CEST)
Cc: Ralf Baechle <ralf@linux-mips.org>, Florian Lohoff <flo@rfc822.org>, linux-mips@linux-mips.org
In-reply-to: <16521.32766.143451.421173@doms-laptop.algor.co.uk>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20040423080247.GC5814@paradigm.rfc822.org> <Pine.LNX.4.55.0404231509190.14494@jurand.ds.pg.gda.pl> <20040423164517.GA16401@linux-mips.org> <Pine.LNX.4.55.0404231849480.14494@jurand.ds.pg.gda.pl> <16521.32766.143451.421173@doms-laptop.algor.co.uk>
Sender: linux-mips-bounce@linux-mips.org
On Fri, 23 Apr 2004, Dominic Sweetman wrote:

> > > The KSU bits are meaningless.  On Indy like most other MIPS systems a
> > > bus error exception may be delayed.  So the generic solution requires
> > 
> >  I beg your pardon?  AFAIK, bus errors are documented to be reported
> > precisely...
> 
> You're both right :-) Data errors like this on an R4x00 are reported
> as cache parity errors, and cache parity error exceptions are precise.
> There's also a signalling mechanism typically used for an invalid
> memory address, which generates a "bus error" exception, which is not
> precise.

 I refer to the situation, when SysCmd(5) is set in a response to a
processor read request.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

<Prev in Thread] Current Thread [Next in Thread>