Re: MC Parity Error

[Dominic Sweetman <dom@mips.com>]

Maciej W. Rozycki (macro@ds2.pg.gda.pl) writes:

> > The KSU bits are meaningless.  On Indy like most other MIPS systems a
> > bus error exception may be delayed.  So the generic solution requires
> 
>  I beg your pardon?  AFAIK, bus errors are documented to be reported
> precisely...

You're both right :-) Data errors like this on an R4x00 are reported
as cache parity errors, and cache parity error exceptions are precise.
There's also a signalling mechanism typically used for an invalid
memory address, which generates a "bus error" exception, which is not
precise.

--
Dominic Sweetman
MIPS Technologies.