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Re: MC Parity Error

To: "Maciej W. Rozycki" <>
Subject: Re: MC Parity Error
From: Dominic Sweetman <>
Date: Fri, 23 Apr 2004 13:43:42 -0700
Cc: Ralf Baechle <>, Florian Lohoff <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <>
Maciej W. Rozycki ( writes:

> > The KSU bits are meaningless.  On Indy like most other MIPS systems a
> > bus error exception may be delayed.  So the generic solution requires
>  I beg your pardon?  AFAIK, bus errors are documented to be reported
> precisely...

You're both right :-) Data errors like this on an R4x00 are reported
as cache parity errors, and cache parity error exceptions are precise.
There's also a signalling mechanism typically used for an invalid
memory address, which generates a "bus error" exception, which is not

Dominic Sweetman
MIPS Technologies.

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