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Re: MC Parity Error

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: MC Parity Error
From: Dominic Sweetman <dom@mips.com>
Date: Fri, 23 Apr 2004 13:43:42 -0700
Cc: Ralf Baechle <ralf@linux-mips.org>, Florian Lohoff <flo@rfc822.org>, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.55.0404231849480.14494@jurand.ds.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20040423080247.GC5814@paradigm.rfc822.org> <Pine.LNX.4.55.0404231509190.14494@jurand.ds.pg.gda.pl> <20040423164517.GA16401@linux-mips.org> <Pine.LNX.4.55.0404231849480.14494@jurand.ds.pg.gda.pl>
Sender: linux-mips-bounce@linux-mips.org
Maciej W. Rozycki (macro@ds2.pg.gda.pl) writes:

> > The KSU bits are meaningless.  On Indy like most other MIPS systems a
> > bus error exception may be delayed.  So the generic solution requires
> 
>  I beg your pardon?  AFAIK, bus errors are documented to be reported
> precisely...

You're both right :-) Data errors like this on an R4x00 are reported
as cache parity errors, and cache parity error exceptions are precise.
There's also a signalling mechanism typically used for an invalid
memory address, which generates a "bus error" exception, which is not
precise.

--
Dominic Sweetman
MIPS Technologies.



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