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Re: MC Parity Error

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: MC Parity Error
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 23 Apr 2004 19:11:36 +0200 (CEST)
Cc: Florian Lohoff <flo@rfc822.org>, linux-mips@linux-mips.org
In-reply-to: <20040423164517.GA16401@linux-mips.org>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20040423080247.GC5814@paradigm.rfc822.org> <Pine.LNX.4.55.0404231509190.14494@jurand.ds.pg.gda.pl> <20040423164517.GA16401@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Fri, 23 Apr 2004, Ralf Baechle wrote:

> > > success report for the MC Bus Error handler :)
> > > 
> > > Apr 19 23:17:32 resume kernel: MC Bus Error
> > > Apr 19 23:17:32 resume kernel: CPU error 0x380<RD PAR > @ 0x0f4c6308
> > > Apr 19 23:17:32 resume kernel: Instruction bus error, epc == 2accf310, ra 
> > > == 2accf2c8
> > > 
> > > I guess i have bad memory. The interesting point is that the machine
> > > continued to run for another 2 days. Shouldnt a memory error halt the
> > > machine ?
> > 
> >  As it happened in the user mode, I'd expect only the victim process to be
> > killed.
> 
> The KSU bits are meaningless.  On Indy like most other MIPS systems a
> bus error exception may be delayed.  So the generic solution requires

 I beg your pardon?  AFAIK, bus errors are documented to be reported
precisely and my past experience with the systems I use confirms this.  
Otherwise bits in <asm/paccess.h> wouldn't work, but they do.  Of course
this is true for errors happening on read transactions (I have troubles
imagining a delayed read), but the semantics of the exception is defined
only for reads anyway.  For other transactions a general-purpose interrupt
should be used (and normally is).  Such an interrupt can happen any time,
indeed (but here it was an IBE, not an interrupt).

> tracking down the actual user, something which in the current kernel is
> relativly easy due to rmap.

 Well, that may be tough anyway -- imagine an uncorrectable memory error 
on a DMA transaction. ;-)

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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