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inconsistent operand constraints in 'asm' in unaligned.h:66 using gcc 3.

To: <linux-mips@linux-mips.org>
Subject: inconsistent operand constraints in 'asm' in unaligned.h:66 using gcc 3.4
From: "Bradley D. LaRonde" <brad@laronde.org>
Date: Thu, 22 Apr 2004 23:22:40 -0400
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
gcc 3.4 complians about:

include/asm/unaligned.h:66: error: inconsistent operand constraints in an
`asm'

from linux CVS 2.4 branch.  That's:

/*
 * Store doubleword ununaligned.
 */
static inline void __stq_u(unsigned long __val, unsigned long long * __addr)
{
        __asm__("usw\t%1, %0\n\t"
                "usw\t%D1, 4+%0"
                : "=m" (*__addr)
                : "r" (__val));
}

I was baffled by the "%D1" syntax until Thiemo Seufer pointed out that %D1
assembled to "one register higher than the register chosen for %1".
Ooooookay.  But gcc complains about a constraint problem.  Maybe "r" and
"%Dn" don't get along (long)?

Anyway... what about __val's type?  I would expect that to be "unsigned long
long" for -mabi=32.  Otherwise will "%D" get what the asm author expected?
If I do change it to "unsigned long long" then I get two of the constraint
errors.  Ooooookay.  Anyone got a constraint that means "consecutive
register pair"?

I finally decided to punt and write:

static inline void __stq_u(unsigned long long __val, unsigned long long *
__addr)
{
        *__addr = __val;
}

Is this OK?  Is there a better solution?


Regards,
Brad


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