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[RFC] Support cpu timer for SMP case

To: linux-mips@linux-mips.org
Subject: [RFC] Support cpu timer for SMP case
From: Jun Sun <jsun@mvista.com>
Date: Tue, 20 Apr 2004 15:23:06 -0700
Cc: jsun@mvista.com
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
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This patch illustrates that the cpu timer can be used as
system timer on a SMP system:

1) count/compare on CPU 0 registers are used to generate 
   jiffy interrupts

2) at the end of processing jiffy interrupt, cpu 0 sends
   a special inter-processor interrupt (IPI) to all other
   cpus and make them do process accounting stuff 
   (local_timer_interrupt()).

3) count registers on all CPU 0 are sync'ed up at the beginning.
   As a result we will have a consistent time reading on 
   all CPUs (do_gettimeofday()).

This patch assumes that the count registers on different CPUs
don't drift from each other after they sync up.  If they do drift,
we can change the code to allow periodic sync up.  We can
probably even support different count frequencies.

This patch is actually tested to be working on sibyte boards.

As a by-product of the patch we also fix a "gettimeofday() going backward"
problem on those smp boards.

Jun

P.S., the patch really looks more complicated than it should be, because
        I am leaving the old time code for the board there but "ifdef"ed out.
        If we make a complete transition to cpu timer, all the ifdef's and
        old time code for the board should go away.

Attachment: 040420.a-cpu-timer-for-smp.patch
Description: Text document

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