| To: | Ashley Evans <ashley@seamlessrecruitment.com> |
|---|---|
| Subject: | Re: R4400MC |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Thu, 15 Apr 2004 04:57:08 +0200 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <407D5CDA.6070407@seamlessrecruitment.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <407BC212.8000303@seamlessrecruitment.com> <20040414125200.GA9206@linux-mips.org> <407D5CDA.6070407@seamlessrecruitment.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Wed, Apr 14, 2004 at 04:46:34PM +0100, Ashley Evans wrote: > Thanks, just thought I'd ask. > > I believe it's the cache controller that's the problem? I don't have the > skills to do it myself but if somebody could explain the issue i'd like > to know? No, the cache controller is really the same as in the SC CPU which is already supported. The problem is everything else around the CPU ... Ralf |
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