On Wed, Mar 31, 2004 at 10:39:19AM -0500, Lijun Chen wrote:
> Thanks a lot, Dominic and Ralf.
> So interrupts and a few exception conditions are maskable and preemptable.
> The machine-level exceptions are non-maskable.If ever multiple
> exceptions occur
> at the same time, cpu picks the highest priority one.
> But in the MIPS64 spec, it says the EXL bit is set when any exception
> other than Reset,
> Soft reset, NMI or Cache Error exception are taken. Does this mean Cache
> error can
> preempt whatever else is going on except for Reset and NMI?
I think so. Usually when cache error happens you are dead.
For bcm1250 there is a cache error handler which works around a hw bug.
I believe the workaround code is in the linux-mips.org tree.
> My intention is to write some information to a kernel buffer when cache
> and bus
> error exceptions occur. If they use the common buffer and a spin_lock()
> is used before
> writing, will this cause dead lock if kernel is handling bus error while
> a cache error
It will be a deadlock only if another exception happens and you try
to acquire the lock while you are already in the middle of
You should use spin_lock() in a scope as small as possible.
BTW, you may my tiby tracing patch handy for something like this.